MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1160

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
18.4.2
Both INTx and message signaled interrupts (MSI) are supported; however there are subtle differences
depending on whether the PCI Express controller is configured as an RC or EP device.
18.4.2.1
18.4.2.1.1
Hardware INTx message generation is not supported in EP mode.
18.4.2.1.2
In EP mode, the PCI Express controller can be configured to automatically generate MSI transactions to
the root complex when an interrupt event occurs. The PCI Express controller uses irq_out (an internal
version of the IRQ_OUT signal) to trigger the generation of the MSI. To trigger the MSI, interrupt events
must be routed to the to irq_out by setting the EP (external pin) bit in the associated Interrupt Destination
register in the PIC. Note that the IRQ_OUT signal should not be used for any other function if it is being
used to trigger MSI transactions.
The remote root complex is expected set up the MSI capability structure of all endpoints at system
initialization by filling the Message Address and Message Data registers with appropriate values and
setting the MSIE bit in the MSI Message Control register.
With the PCI Express controller properly configured, when it detects the leading edge of irq_out going
active, it generates a PCI Express memory write transaction to the address specified in the MSI Message
Address register (and MSI Message Upper Address register) with a data payload as specified in the MSI
Message Data register (with leading zeros appended).
18.4.2.1.3
Software can generate outbound assert or deassert INTx message transactions by using the outbound
ATMU mechanism described in
18.4.2.1.4
Host software has to set up the MSI capability registers to enable MSI mode, and have the correct values
for the MSI address and data register. Then local software has to read the MSI address in the MSI
capability register and configure the outbound ATMU window to map the translated address to the MSI
18-106
Power_Indicator_Blink
Power_Indicator_Off
Attention_Button_Pressed
Interrupts
EP Interrupt Generation
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Hardware INTx Message Generation
Hardware MSI Generation
Software INTx Message Generation
Software MSI Generation
Name
Table 18-121. PCI Express EP Inbound Message Handling
0100 0111
0100 0100
Code[7:0]
0100 1000
Section 18.4.1.8.1, “Outbound ATMU Message
Routing[2:0]
100
100
100
Set PEX_PME_MES_DR[PIB] bit. Send interrupt if
enabled.
Set PEX_PME_MES_DR[PIOF] bit. Send interrupt if
enabled.
No action taken
Action
Generation.”
Freescale Semiconductor