MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 90

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Part III, “Memory, Security, and I/O Interfaces,” defines the device’s memory, security, and I/O interfaces
and how these blocks interact with one another and with other blocks on the device. The following chapters
are included:
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Chapter 7, “L2 Look-Aside Cache/SRAM,”
also be addressed directly as memory-mapped SRAM.
Chapter 8, “e500 Coherency Module,”
communication between the e500v2 core complex, the L2 cache, and the other blocks that
comprise the coherent memory domain of the MPC8544E.
The ECM provides a mechanism for I/O-initiated transactions to snoop the core complex bus
(CCB) of the e500v2 core to maintain coherency across cacheable local memory. It also provides
a flexible, easily expandable switch-type structure for e500v2- and I/O-initiated transactions to be
routed (dispatched) to target modules on the MPC8544E.
Chapter 9, “DDR Memory Controller,”
the MPC8544E. This fully programmable controller supports most DDR memories available
today, including both buffered and unbuffered devices. The built-in error checking and correction
(ECC) ensures very low bit-error rates for reliable high-frequency operation. Dynamic power
management and auto-precharge modes simplify memory system design. Special features like
ECC error injection support rapid system debug.
Chapter 10, “Programmable Interrupt Controller,”
interrupt controller (PIC) of the MPC8544E. The PIC is OpenPIC-compliant, provides interrupt
management, and receives hardware-generated interrupts from different sources (both internal and
external), prioritizing them and delivering them to the CPU for servicing.
Chapter 11, “I
This synchronous, serial, bidirectional, multi-master bus allows two-wire connection of devices,
such as microcontrollers, EEPROMs, real-time clock devices, A/D converters and LCDs. The
MPC8544E powers up in boot sequencer mode, which allows the I
configuration registers.
Chapter 12, “Security Engine (SEC)
Chapter 13, “DUART,”
(UARTs) which feature a PC16552D-compatible programming model. These independent UARTs
are provided specifically to support system debugging.
Chapter 14, “Local Bus Controller,”
component of the local bus controller (LBC) is its memory controller which provides a seamless
interface to many types of memory devices and peripherals. The memory controller controls eight
memory banks shared by a high-performance SDRAM machine, a general-purpose chip-select
machine (GPCM), and up to three user-programmable machines (UPMs). As such, it supports a
minimal glue logic interface to synchronous DRAM (SDRAM), SRAM, EPROM, Flash EPROM,
burstable RAM, regular DRAM devices, extended data output DRAM devices, and other
peripherals.
Chapter 15, “Enhanced Three-Speed Ethernet Controllers,”
three-speed Ethernet controllers on the MPC8544E. These controllers provide 10/100/1GByte
Ethernet support with a complete set of media-independent interface options including MII, RMII,
GMII, RGMII, SGMII, TBI, and RTBI. Each controller provides very high throughput using a
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
C Interfaces,”
describes the (dual) universal asynchronous receiver/transmitters
describes the inter-IC (IIC or I
describes the local bus controller of the MPC8544E. The main
2.1,” describes the security controller of the MPC8544E.
defines the e500v2 coherency module and how it facilitates
describes the DDR/DDR2 SDRAM memory controller of
describes the L2 cache. Note that the L2 cache can
describes the embedded programmable
2
describes the two enhanced
C) bus controllers of the MPC8544E.
2
C1 controller to initialize
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