MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 674

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Local Bus Controller

This parameter, controlled by LSDMR[RFRC], defines the earliest timing for an ACTIVATE or

REFRESH command after a REFRESH command to the same SDRAM device.

If the additional delay of any buffers placed on the command strobes (LSDRAS, LSDCAS, LSDWE, and

LSDA10), is endangering the device setup time, LSDMR[BUFCMD] should be set. Setting this bit causes

the memory controller to add LCRR[BUFCMDC] extra bus cycles to the assertion of SDRAM control

signals (LSDRAS, LSDCAS, LSDWE, and LSDA10) for each SDRAM command.

ZZZZZZ RAS ADD

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Refresh Recovery Interval (RFRC)

External Address and Command Buffers (BUFCMD)

Figure 14-41. BUFCMD = 1, LCRR[BUFCMDC] = 2

Command (If Needed)

PRECHARGE ALL

Figure 14-40. RFRC = 4 (6 Clock Cycles)

PRETOACT = 3

AUTO REFRESH

RFRC = 4 (6 Clocks)

Freescale Semiconductor