MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 654

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Local Bus Controller

address during LALE phases. UPM may require LA[27:31] if the LBC is generating its own burst address

To illustrate how a large transaction is handled by the LBC,

performing a 32-byte write starting at address 0x5420. Note that during each of the 32 assertions of LALE,

LA[27:31] exactly mirror LAD[27:31], but during data phases, only LAD[0:7] and LDP[0] are driven with

valid data and parity, respectively.

The three memory controllers in the LBC generate an internal transfer acknowledge signal, TA, to allow

data on LAD[0:31] to be either sampled (for reads) or changed (on writes). The data sampling/data change

always occurs at the end of the bus cycle in which the LBC asserts TA internally. In LBC debug mode, TA

is also visible externally on the MDVAL signal. GPCM and SDRAM controllers automatically generate

TA according to the timing parameters programmed for them in option and mode registers; a UPM

generates TA only when a UPM pattern has the UTA RAM word bit set.

Note: All address and signal values are shown in hexadecimal.

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Data Transfer Acknowledge (TA)

Figure 14-21. Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420

of 32 data bytes, P(Bk) = parity bit of k

Figure 14-21

shows LBC signals for GPCM

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