MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1256

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug Features and Watchpoint Facility
21.4.2
The DDR interface has two debug modes distinguished by which pins drive the debug information. In one
mode, debug information (source ID, data valid) is multiplexed onto the ECC pins; the other mode uses
the debug pins.
21.4.2.1
If MSRCID0 is high when sampled during POR, the debug information from the DDR SDRAM interface
is driven on MSRCID[0:4] and MDVAL. This POR value is captured in PORDBGMSR[MEM_SEL] as
described in
source ID appears on MSRCID[0:4] during a RAS or CAS cycle. During any other cycle, the value of
MSRCID[0:4] is all ones, which indicates idle cycles on the address/command interface. Similarly,
MDVAL is asserted during valid data cycles on the DDR interface.
21.4.2.2
If MSRCID1 is low when sampled during POR, debug information from the DDR SDRAM interface is
selected to appear on MECC[0:5] as shown in
(the source ID), appears on MECC[0:4] during a RAS or CAS cycle. During any other cycle the value of
MECC[0:4] is all ones. A data-valid signal (DVAL) is driven on MECC5 during valid DDR SDRAM data
cycles.
21-26
(Hex)
Value
0C
0D
06
07
08
09
0A
0B
0E
0F
DDR SDRAM Interface Debug
Section 19.4.1.5, “POR Debug Mode Status Register (PORDBGMSR).”
Reserved
Security
Configuration space
Reserved
Boot sequencer
Reserved
Reserved
Reserved
Reserved
Local space (DDR)
Debug Information on Debug Pins
Debug Information on ECC Pins
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
In this mode, MECC[0:5] must be disconnected from all SDRAM devices
to prevent contention on those lines.
Source (or Target) Port
Table 21-26. Source and Target ID Values (continued)
Figure
NOTE
(Hex)
Value
1C
1D
17
18
1A
1B
1E
1F
16
19
21-1. In this mode, the ID value of the source port,
Reserved
System access port (SAP)
eTSEC1
Reserved
eTSEC3
Reserved
Reserved
Reserved
Reserved
Non valid port indicator (reserved for debug info)
Source (or Target) Port
Freescale Semiconductor
In this mode, the