MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 939

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
This advertises to the Link Partner that the TBI supports PAUSE and Full Duplex mode and does not support Half
This enables the TBI to restart Auto-Negotiations using the configuration set in the AN Advertisement register.
Set TBICON comma detect = 1 to allow SerDes to perform code group alignment based upon the detection of
Set up the MII Mgmt for a write cycle to TBI’s AN Advertisement register (write the PHY address and Register
Set up the MII Mgmt for a write cycle to TBI’s Control register (write the PHY address and Register address),
Set up the MII Mgmt for a read cycle to TBI Control register (write the TBI address and Register address),
Set up the MII Mgmt for a write cycle to TBICON register (write the PHY address and Register address),
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
This sets TBI in single clock mode and MII Mode off to enable communication with SerDes.
Writing to MII Mgmt Control with 16-bit data intended for TBI’s AN Advertisement register,
Perform an MII Mgmt read cycle to verify state of TBI Control Register (optional)
The AN Advertisement register is at offset address 0x04 from the TBI’s address.
Table 15-169. SGMII Mode Register Initialization Steps (continued)
Writing to MII Mgmt Control with 16-bit data intended for TBI’s Control register,
(Uses the TBI address and Register address placed in MIIMADD register),
Writing to MII Mgmt Control with 16-bit data intended for TBICON register,
The TBICON register is at offset address 0x11 from the TBI’s address.
(Set TBICON Enable Wrap = 1 to configure SerDes in loopback mode.
read the MIIMSTAT and look for AN Enable and other bit information.
the Control register is at offset address 0x00 from the TBI’s address.
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
The TBI Control register is at offset address 0x0 from TBIPA.
MIIMCON[0000_0000_0000_0000_0000_0000_0010_0000]
MIIMCON[0000_0000_0000_0000_0000_0001_1010_0000]
MIIMCON[0000_0000_0000_0000_0001_0010_0000_0000]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
MIIMADD[0000_0000_0000_0000_0001_0000_0001_0001]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0100]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
This indicates that the eTSEC MII Mgmt bus is idle.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed.
Check to see if MII Mgmt write is complete.
Check to see if MII Mgmt write is complete.
Perform an MII Mgmt write cycle to TBI.
Perform an MII Mgmt write cycle to TBI.
Perform an MII Mgmt write cycle to TBI.
Additional SerDes setup as required
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY] = 0,
Duplex mode.
address),
comma.)
Enhanced Three-Speed Ethernet Controllers
15-207