MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 809

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

15.5.3.5.12 Interface Status Register (IFSTAT)

Figure 15-47

15.5.3.5.13 MAC Station Address Part 1 Register (MACSTNADDR1)

The MACSTNADDR1 register is written by the user. The value of the station address written into

MACSTNADDR1 and MACSTNADDR2 is byte reversed from how it would appear in the DA field of a

frame in memory. For example, for a station address of 0x12345678ABCD, MACSTNADDR1 is set to

0xCDAB7856 and MACSTNADDR2 is set to 0x34120000.

Freescale Semiconductor

Offset eTSEC1:0x2_453C; eTSEC3:0x2_553C

Excess Defer Excessive transmission defer. This bit latches high and is cleared when read. This bit is cleared by

describes the fields of the FSTAT register.

shows the IFSTAT register.

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Not Valid Not valid.

0 Normal operation.

1 The MAC excessively defers a transmission.

0 MII Mgmt read cycle has completed and the read data is valid.

1 MII Mgmt read cycle has not completed and the read data is not yet valid.

Scan in progress.

0 A scan operation (continuous MII Mgmt read cycles) is not in progress.

1 A scan operation (continuous MII Mgmt read cycles) is in progress.

0 MII Mgmt block is not currently performing an MII Mgmt read or write cycle.

1 MII Mgmt block is currently performing an MII Mgmt read or write cycle.

Figure 15-47. Interface Status Register Definition

Table 15-49. MIIMIND Field Descriptions

Table 15-50. IFSTAT Field Descriptions

Excess Defer

Enhanced Three-Speed Ethernet Controllers

Access: Read only