MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 329

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The following sections describe the DDR SDRAM controller input and output signals, the meaning of their

different states, and relative timing information for assertion and negation.

Freescale Semiconductor

describes the DDR controller memory interface signals.

Detailed Signal Descriptions

Memory Interface Signals

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

I/O Data bus. Both input and output signals on the DDR memory controller.

Table 9-3. Memory Interface Signals—Detailed Signal Descriptions

As outputs for the bidirectional data bus, these signals operate as described below.

As inputs for the bidirectional data bus, these signals operate as described below.

Timing Assertion/Negation—Driven coincident with corresponding data strobes (MDQS) signal.

Timing Assertion/Negation—The DDR SDRAM drives data during a READ transaction.

Table 9-2. Memory Address Signal Mappings (continued)

Asserted/Negated—Represent the value of data being driven by the DDR memory controller.

High impedance—No READ or WRITE command is in progress; data is not being driven by

Asserted/Negated—Represents the state of data being driven by the external DDR

High impedance—No READ or WRITE command in progress; data is not being driven by the

Auto-precharge for DDR signaled on A10 when

DDR_SDRAM_CFG[PCHB8] = 0

Auto-precharge for DDR signaled on A8 when

DDR_SDRAM_CFG[PCHB8] = 1

the memory controller or the DRAM.

memory controller or the DRAM.

JEDEC DDR DIMM Signals

DDR Memory Controller