MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1171

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Freescale Semiconductor

2:1 CCB to SYSCLK clock ratio may not be selected when PCI_clk_sel are configured to run off of SYSCLK.

Offset 0xE_0000

Reset 0 0 0 0 0 0 0

PCI_clk_sel Clock used for PCI. This bit corresponds to the values on cfg_pci_clk_sel at the negation of HRESET:

describes the bit settings of PORPLLSR.

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Clock ratio between the e500 core and the CCB clock. The 3 lsbs of this field correspond to the values

on cfg_core_pll[0:2] at the negation of HRESET. Patterns not shown are reserved.

0 PCI runs off of PCI_CLK

1 PCI runs off of SYSCLK

Clock ratio between the CCB (platform) clock and SYSCLK. The 4 lsbs correspond to the values on

cfg_sys_pll[0:3] at the negation of HRESET. Patterns not shown are reserved.

Figure 19-1. POR PLL Status Register (PORPLLSR)

0 n n n n n n

Table 19-4. PORPLLSR Field Descriptions

Access: Read Only

Global Utilities