MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1024

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

PCI Bus Interface

17.3.2.16 PCI Bus Interrupt Pin Register

The programmable interrupt controller (PIC) has 12 general purpose interrupt request inputs (IRQ[0:11])

and an interrupt output, IRQ_OUT (active low, level sensitive), to which all external and most internal

interrupt sources (including PCI) can be routed. IRQ_OUT is mapped to PCI_INTA as a default. Note that

this device does not respond to INTACK or special cycle commands on the PCI interfaces.

17.3.2.17 PCI Bus Minimum Grant Register (MIN_GNT)

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Specifies the length of the device’s burst period (0x00 indicates that this PCI controller has no

major requirements for the settings of latency timers.)

Interrupt pin

Table 17-43. PCI Bus Minimum Grant Register Field Description

7–0 Interrupt Line Used to communicate interrupt line routing information.

Table 17-41. PCI Bus Interrupt Line Register Field Description

Table 17-42. PCI Bus Interrupt Pin Register Field Description

Figure 17-44. PCI Bus Minimum Grant Register (MIN_GNT)

Figure 17-43. PCI Bus Interrupt Pin Register

PCI_INTA pin selected

Interrupt Pin

Freescale Semiconductor

Access: Read only