MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1242

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Debug Features and Watchpoint Facility

Offset 0x004

NECEN Not equal context enable. Qualifies the matching of current context with programmed context as a watchpoint

SIDEN Source ID enable

TIDEN Target ID enable

STRT Start condition. Specifies the event that arms the watchpoint monitor to start looking for the programmed

shows WMCR1.

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

event criterion, as written in the context registers described in

0 The failure of a current context match does not affect watchpoint event detection

1 Watchpoint events are qualified with NOT getting a current context compare with the programmed context

Note: ECEN and NECEN must not be enabled in the same run. If both are set, watchpoint events are

0 Source ID does not affect watchpoint event detection.

1 Watchpoint events are qualified by comparison with the programmed WMCR1(SID) value.

0 Target ID does not affect watchpoint event detection.

1 Watchpoint events are qualified by comparison with the programmed WMCR1(TID) value.

000 No event. Armed immediately

001 Trace buffer event is detected

010 Performance monitor signals overflow

011 TRIG_IN transitions from 0 to 1

100 TRIG_IN transitions from 1 to 0

101 Current context ID equals programmed context ID

110 Current context ID is not equal to programmed context ID

111 Reserved

event value.

inhibited (never occur).

Figure 21-3. Watchpoint Monitor Control Register 1 (WMCR1)

Table 21-7. WMCR0 Field Descriptions (continued)

Section 21.3.3, “Context ID Registers.”

Freescale Semiconductor

Access: Read/Write