MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 614
MPC8544COMEDEV
Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544COMEDEV
Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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DUART
Table 13-19
13.3.1.13
The DMA status registers (UDSRs) are read-only registers that return transmitter and receiver FIFO status.
UDSRs also provide the ability to assist DMA data operations to and from the FIFOs.
Figure 13-15
Table 13-20
13-18
Bits
Bits
0–5
0–5
6
7
6
7
Offset 0x510
Reset
Name
RXRDY Receiver ready. This read-only bit reflects the status of the receiver FIFO or URBR. The status depends on
TXRDY Transmitter ready. This read-only bit reflects the status of the transmitter FIFO or the UTHR. The status
Name
CW
BO
W
—
R
—
describes the fields of the UAFRs.
0x610
describes the fields of the UDSRs.
shows the bits in UDSRs.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved.
Baud clock select.
0 The baud clock is not gated off.
1 The baud clock is gated off.
Concurrent write enable.
0 Disables writing to both UART0 and UART1
1 Enables concurrent writes to corresponding UART registers. A write to a register in UART0 is also a write
DMA Status Registers (UDSR0, UDSR1)
Reserved
depends on the DMA mode selected, which is determined by the DMS and FEN bits in the UFCR.
0 The bit is cleared, as shown in
1 This bit is set, as shown in
the DMA mode selected, which is determined by the DMS and FEN bits in the UFCR.
0 The bit is cleared, as shown in
1 This bit is set, as shown in
to the corresponding register in UART1 and vice versa. The user needs to ensure that the LCR[DLAB] of
both UARTs are in the same state before executing a concurrent write to register addresses 0x500, 0x501
and 0x502.
0
0
0
Figure 13-15. DMA Status Register (UDSR)
Table 13-19. UAFR Field Descriptions
Table 13-20. UDSR Field Descriptions
0
Table
Table
Table
Table
—
13-21.
13-23.
13-22.
13-24.
0
Description
Description
0
0
5
TXRDY
Freescale Semiconductor
0
6
Access: Read only
RXRDY
1
7
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