MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1053

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.5.2
Whenever data must cross a bridge between two busses, the byte ordering of data on the source and
destination buses must be considered. The internal platform bus of this device is inherently big endian and
the PCI bus interface is inherently little endian.
There are two methods to handle ordering of data as it crosses a bridge—address invariance and data
invariance. Address invariance preserves the addressing of bytes within a scalar data element, but not the
relative significance of the bytes within that scalar. Conversely, data invariance preserves the relative
significance of bytes within a scalar, but not the addressing of the individual bytes that make up a scalar.
This device uses address invariance as its byte ordering policy.
As stated above, address invariance preserves the byte address of each byte on an I/O interface as it is
placed in memory or moved into a register. This policy can have the effect of reversing the significance
order of bytes (most significant to least significant and vice versa), but it has the benefit of preserving the
format of general data structures. Provided that software is aware of the endianness and format of the data
structure, it can correctly interpret the data on either side of the bridge.
Figure 17-61
address invariant bridge to a little endian destination.
Note that although the significance of the bytes within the scalar have changed, the address of the
individual bytes that make up the scalar have not changed. As long as software is aware that the source of
the data used a big endian format, the data can be interpreted correctly.
Figure 17-63
Freescale Semiconductor
Address lsbs
Address lsbs
Significance
Significance
Byte lane
Byte lane
Byte Ordering
Data
Data
shows the transfer of a 4-byte scalar, 0x4142_4344, from a big endian source across an
shows data flowing the other way, from a little endian source to a big endian destination.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 17-61. Address Invariant Byte Ordering—4 bytes Outbound
Figure 17-62. Address Invariant Byte Ordering—4 bytes Inbound
MSB
MSB
000
011
41
41
0
3
Little endian
source bus
source bus
Big endian
001
010
42
42
1
2
010
001
43
43
2
1
LSB
LSB
011
000
44
44
3
0
MSB
MSB
011
000
44
44
3
0
destination bus
destination bus
Little endian
Big endian
010
001
43
43
2
1
001
010
42
42
1
2
LSB
LSB
000
011
41
41
0
3
PCI Bus Interface
17-69