HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 97

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.3.2
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3
After reset release, MSTPCRA to MSTPCRC are initialized to H'3F, H'FF, and H'FF, respectively,
and all modules except the DTC enter module stop mode. Consequently, on-chip supporting
module registers cannot be read or written to. Register reading and writing is enabled when the
module stop mode is exited.
Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled: Cannot be Used
RES
Address bus
RD
HWR, LWR
D15 to D0
(1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5)
(6)
Note: * Three program wait states are inserted.
φ
Interrupts after Reset
State of On-Chip Supporting Modules after Reset Release
Start address ((5)=(2)(4))
First program instruction
(1)
*
in this LSI)
Vector fetch
(2)
High
Rev. 7.00 Sep. 11, 2009 Page 61 of 566
*
(3)
(4)
Internal
processing
Section 4 Exception Handling
Prefetch of first
program instruction
*
(5)
REJ09B0211-0700
(6)