HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 131
HD64F2612FA20
Manufacturer Part Number
HD64F2612FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2612FA20
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
43
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2612FA20
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F2612FA20J
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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6.4
6.4.1
PBC operation can be disabled or enabled using the module stop control register. The initial
setting is for PBC operation to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 20, Power-Down Modes.
6.4.2
The PC break interrupt is shared by channels A and B. The channel from which the request was
issued must be determined by the interrupt handler.
6.4.3
The CMFA and CMFB flags are not automatically cleared to 0, so 0 must be written to CMFA or
CMFB after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt
will be requested after interrupt handling ends.
6.4.4
A PC break interrupt generated when the DTC is the bus master is accepted after the bus has been
transferred to the CPU by the bus controller.
6.4.5
When a PC break is set for an instruction fetch at an address following a BSR, JSR, JMP, TRAPA,
RTE, or RTS instruction:
Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS
instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the
instruction fetch at the next address.
6.4.6
When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC break interrupt
becomes valid two states after the end of the executing instruction. If a PC break interrupt is set
for the instruction following one of these instructions, since interrupts, including NMI, are
disabled for a 3-state period in the case of LDC, ANDC, ORC, and XOR, the next instruction is
always executed. For details, see section 5, Interrupt Controller.
Usage Notes
Module Stop Mode Setting
PC Break Interrupts
CMFA and CMFB
PC Break Interrupt when DTC is Bus Master
PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA,
RTE, or RTS Instruction
I Bit Set by LDC, ANDC, ORC, or XORC Instruction
Rev. 7.00 Sep. 11, 2009 Page 95 of 566
Section 6 PC Break Controller (PBC)
REJ09B0211-0700
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