HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 451

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit Rate and Bit Timing Settings: The bit rate and bit timing settings are made in the bit
configuration register (BCR). Settings should be made such that all CAN controllers connected to
the CAN bus have the same baud rate and bit width. The 1-bit time consists of the total of the
settable time quantum (tq).
SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal
bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical
delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This
segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer
segment for correcting phase drift (negative). This segment is shortened when synchronization
(resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, sample
point, and SJW) are shown in table 15.2.
Table 15.2 Limits for Settable Value
Name
Time segment 1
Time segment 2
Baud rate prescaler
Bit sample point
Re-synchronization jump width
Notes: 1. SJW is stipulated in the CAN specifications:
2. The minimum value of TSEG2 is stipulated in the CAN specifications:
3. The minimum value of TSEG1 is stipulated in the CAN specifications:
3 ≥ SJW ≥ 0
TSEG2 ≥ SJW
TSEG1 > TSEG2
1 time quantum
SYNC_SEG
Figure 15.8 Detailed Description of One Bit
1-bit time (8 to 25 time quanta)
PRSEG
Time segment 1 (TSEG1)
4 to 16 time quanta
Abbreviation
TSEG1
TSEG2
BRP
BSP
SJW *
1
Section 15 Controller Area Network (HCAN)
PHSEG1
Rev. 7.00 Sep. 11, 2009 Page 415 of 566
Min Value
B'0011 *
B'001 *
B'000000
B'0
B'00
2 to 8 time quanta
Time segment 2
3
2
(TSEG2)
PHSEG2
REJ09B0211-0700
Max Value
B'1111
B'111
B'111111
B'1
B'11