HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 315

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.8.4
Input Level Detection: When the input condition set in ICSR occurs on any one of the POE pins,
the MMT output pins go to the high-impedance state.
• Pins placed in the high-impedance state (the MMT’s output pins)
Note: When used as an output port or TPU output pin, a pin will not enter the high-impedance
1. Falling edge detection
2. Low level detection
Exiting High-Impedance State: The MMT output pins that have entered the high-impedance
state are released from this state by restoring them to their initial states by means of a power-on
reset, or by clearing all the POE flags in ICSR (POE0F to POE3F: bits 12 to 15).
The 7 pins PWOB, PWOA, PVOB, PVOA, PUOB, PUOA, PCO are placed in the high-
impedance state.
When a transition from high- to low-level input occurs on a POE pin.
Figure 11.22 shows the low level detection operation. Low level sampling is performed 16
times in succession using the sampling clock set in ICSR. The input is not accepted if a high
level is detected even once among these samples.
The timing of entry of the MMT's output pins into the high-impedance state from the sampling
clock is the same for falling edge detection and low level detection.
Sampling clock
POE input
PUOA
All samples low-level
At least one high-level
sample
Note: The other MMT output pins also go to the high-impedance state at the same timing.
φ
state.
Operation
Figure 11.22 Low Level Detection Operation
[1]
[1]
8, 16, or
128 clocks
[2]
[2]
Section 11 Motor Management Timer (MMT)
Rev. 7.00 Sep. 11, 2009 Page 279 of 566
[3]
[16] Flag set (POE accepted)
[13]
High-impedance state
Flag not set
REJ09B0211-0700