HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 459

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

• Remote frame reception
Unread Message Overwrite: If the receive message identifier matches the mailbox identifier, the
receive message is stored in the mailbox regardless of whether the mailbox contains an unread
message or not. If a message overwrite occurs, the corresponding bit (UMSR0 to UMSR15) is set
in the unread message register (UMSR). In overwriting an unread message, when a new message
is received before the corresponding bit in the receive complete register (RXPR) has been cleared,
the unread message register (UMSR) is set. If the unread interrupt flag (IRR9) in the interrupt
mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the
CPU. Figure 15.12 shows a flowchart for unread message overwriting.
remaining mailboxes. It is therefore possible for a message matching mailbox 0 to be received
by another mailbox. Note that the same message cannot be stored in more than one of
mailboxes 1 to 15. On receiving a message, a CPU interrupt request may be generated
depending on the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR)
settings.
Two kinds of messages—data frames and remote frames—can be stored in mailboxes. A
remote frame differs from a data frame in that the remote transmission request bit (RTR) in the
message control register and the data field are 0 bytes long. The data length to be returned in a
data frame must be stored in the data length code (DLC) in the control field.
When a remote frame (RTR = recessive) is received, the corresponding bit is set in the remote
request wait register (RFPR). If the corresponding bit (MBIMR0 to MBIMR15) in the mailbox
interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the
interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can
be sent to the CPU.
Section 15 Controller Area Network (HCAN)
Rev. 7.00 Sep. 11, 2009 Page 423 of 566
REJ09B0211-0700