HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 403

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.7.4
In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372,
or 256 times the transfer rate (fixed at 16 times in normal asynchronous mode) as determined by
bits BCP1 and BCP0. In reception, the SCI samples the falling edge of the start bit using the basic
clock, and performs internal synchronization. As shown in figure 14.25, by sampling receive data
at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at
the middle of the bit. The reception margin is given by the following formula.
Where M: Reception margin (%)
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
M = | (0.5 −
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
M = (0.5 – 1/2 × 372) × 100%
Receive Data Sampling Timing and Reception Margin in Smart Card Interface
Mode
= 49.866%
2N
1
) − (L − 0.5) F −
| D − 0.5 |
Section 14 Serial Communication Interface (SCI)
N
Rev. 7.00 Sep. 11, 2009 Page 367 of 566
(1 + F) | × 100%
REJ09B0211-0700