HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 468

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 15 Controller Area Network (HCAN)
15.8.10 HCAN TXCR Operation
1.
• The HRxD pin is stacked to 1 because of a CAN bus error, etc.
• There is at least one mailbox waiting for transmission or being transmitted.
• The message transmission in a mailbox being transmitted is canceled by TXCR.
To avoid this, one of the following countermeasures must be executed.
• Transmission must not be canceled by TXCR. When transmission is normally completed after
• To cancel transmission, the corresponding bit to TXCR must be written to 1 continuously until
2. When the bus-off state is entered while TXPR is set and the transmit wait state is entered, the
• A transmit wait message must be cleared by resetting the HCAN during the bus-off period.
Rev. 7.00 Sep. 11, 2009 Page 432 of 566
REJ09B0211-0700
If this occurs, transmission is canceled. However, since TXPR and TXCR states are indicated
wrongly that a message is being cancelled, transmission cannot be restarted even if the stack
state of the HRxD pin is canceled and the CAN bus recovers the normal state. If there are at
least two transmission messages, a message which is not being transmitted is canceled and a
message being transmitted retains its state.
the CAN bus has recovered, TXPR is cleared and the HCAN recovers the normal state.
the bit becomes 0. TXPR and TXCR are cleared and the HCAN recovers the normal state.
internal state machine does not operate even if TXCR is set during the bus-off state. Therefore
transmission cannot be canceled. The message can be canceled when one message is
transmitted or a transmission error occurs after the bus-off state is recovered. To clear a
message after the bus-off state is recovered, the following countermeasure must be executed.
To reset the HCAN, the module stop bit (MSTPC3 in MSTPCRC) must be set or cleared. In
this case, the HCAN is entirely reset. Therefore the initial settings must be made again.
When the transmit wait cancel register (TXCR) is used to cancel a transmit wait message in a
transmit wait mailbox, the corresponding bit to TXCR and the transmit wait register (TXPR)
may not be cleared even if transmission is canceled. This occurs when the following
conditions are all satisfied.