HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 285

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.3.2
The timer control register (TCNR) controls the enabling or disabling of interrupt requests, selects
the enabling or disabling of register access, selects counter operation or halting, and controls the
enabling or disabling of toggle output synchronized with the PWM period.
Bit
7
6
5
4 to 2 —
1
0
Bit Name
—
CST
RPRO
TGIEN
TGIEM
Timer Control Register (TCNR)
Initial Value
0
0
0
All 0
0
0
R/W
R/W
R/W
R/W
—
R/W
R/W
Description
Reserved
This bit is always read as 0. Only 0 should be written
to this bit.
Timer Counter Start
Selects operation or halting of the timer counter
(TCNT) and timer dead time counter (TDCNT).
0: TCNT and TDCNT operation is halted
1: TCNT and TDCNT perform count operations
Register Protect
Enables or disables the reading of registers other
than TSR, and enables or disables writes to registers
other than TBRU to TBRW, TPBR, and TSR. Writes
to TCNR itself are also disabled. Note that reset input
is necessary in order to write to these registers again.
0: Register access enabled
1: Register access disabled
Reserved
These bits are always read as 0. Only 0 should be
written to these bits.
TGR Interrupt Enable N
Enables or disables interrupt requests by the TGFN
bit when TGFN is set to 1 in the TSR register.
0: Interrupt requests by TGFN bit disabled
1: Interrupt requests by TGFN bit enabled
TGR Interrupt Enable M
Enables or disables interrupt requests by the TGFM
bit when TGFM is set to 1 in the TSR register.
0: Interrupt requests by TGFM bit disabled
1: Interrupt requests by TGFM bit enabled
Section 11 Motor Management Timer (MMT)
Rev. 7.00 Sep. 11, 2009 Page 249 of 566
REJ09B0211-0700