HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 93

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.1
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Exception sources, the stack
structure, and operation of the CPU vary depending on the interrupt control mode. For details on
the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1
Priority
High
Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
4.2
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses. Since the usable modes differ depending on the product, for
details on each product, refer to section 3, MCU Operating Modes.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
3. Trap instruction exception handling requests are accepted at all times in program
Exception Sources and Exception Vector Table
Exception Handling Types and Priority
Exception Type
Reset
Trace *
Direct transition
Interrupt
Trap instruction *
executed after execution of an RTE instruction.
instruction execution, or on completion of reset exception handling.
execution state.
Exception Types and Priority
1
Section 4 Exception Handling
3
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES pin,
or when the watchdog timer overflows. The CPU enters the
reset state when the RES pin is low.
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in the EXR is set to 1.
Starts when a direction transition occurs as the result of SLEEP
instruction execution.
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued *
Started by execution of a trap instruction (TRAPA).
Rev. 7.00 Sep. 11, 2009 Page 57 of 566
Section 4 Exception Handling
REJ09B0211-0700
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