HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 466

IC H8S MCU FLASH 128K 80QFP

HD64F2612FA20

Manufacturer Part Number
HD64F2612FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2612FA20

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
43
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2612FA20
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F2612FA20J
Manufacturer:
RENESAS/瑞萨
Quantity:
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Section 15 Controller Area Network (HCAN)
15.7
A bus transceiver IC is necessary to connect this chip to a CAN bus. A Philips PCA82C250
transceiver IC is recommended. Any other product must be compatible with the PCA82C250.
Figure 15.16 shows a sample connection diagram.
15.8
15.8.1
HCAN operation can be disabled or enabled using the module stop control register. The initial
setting is for HCAN operation to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 20, Power-Down Modes.
15.8.2
The HCAN is reset by a power-on reset, in hardware standby mode, and in software standby
mode. All the registers are initialized in a reset, however mailboxes (message control
(MCx[x])/message data (MDx[x])) are not. After power-on, mailboxes (message control
(MCx[x])/message data (MDx[x])) are un-initialized, and their values are undefined. Therefore,
mailbox initialization must always be carried out after a power-on reset, a transition to hardware
standby mode, or software standby mode. The reset interrupt flag (IRR0) is always set after a
power-on reset or recovery from software standby mode. As this bit cannot be masked in the
interrupt mask register (IMR), if HCAN interrupt enabling is set in the interrupt controller without
clearing the flag, an HCAN interrupt will be initiated immediately. IRR0 should therefore be
cleared during initialization.
Rev. 7.00 Sep. 11, 2009 Page 430 of 566
REJ09B0211-0700
CAN Bus Interface
Module Stop Mode Setting
Reset
Usage Notes
This LSI
Figure 15.16 High-Speed Interface Using PCA82C250
HRxD
HTxD
Note: NC: No Connection
NC
PCA82C250
RS
RxD
TxD
Vref
CANH
CANL
GND
Vcc
Vcc
124 Ω
124 Ω
CAN bus

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