HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 71

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 2.5
Instruction
AND
OR
XOR
NOT
Note:
Table 2.6
Instruction
SHAL
SHAR
SHLL
SHLR
ROTL
ROTR
ROTXL
ROTXR
Note:
* Refers to the operand size.
* Refers to the operand size.
B: Byte
W: Word
L: Longword
B: Byte
W: Word
L: Longword
Logic Operations Instructions
Shift Instructions
Size *
B/W/L
B/W/L
B/W/L
B/W/L
Size *
B/W/L
B/W/L
B/W/L
B/W/L
Function
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
¬ Rd → Rd
Takes the one's complement of general register contents.
Function
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shifts are possible.
Rd (shift) → Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shifts are possible.
Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotations are possible.
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotations are possible.
Rev. 7.00 Sep. 11, 2009 Page 35 of 566
REJ09B0211-0700
Section 2 CPU