HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 306

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 11 Motor Management Timer (MMT)
11.7
11.7.1
MMT operation can be disabled or enabled using the module stop control register. The initial
setting is for MMT operation to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 20, Power-Down Modes.
11.7.2
Note that the kinds of operation and contention described below occur during MMT operation.
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T
the buffer register to the compare register (TGR or TPDR) by a buffer operation. The data
transferred is the buffer register write data.
Figure 11.17 shows the timing in this case.
Rev. 7.00 Sep. 11, 2009 Page 270 of 566
REJ09B0211-0700
2
state of a buffer register (TBRU to TBRW, or TPBR) write cycle, data is transferred from
Figure 11.17 Contention between Buffer Register Write and Compare Match
Usage Notes
Notes for MMT Operation
Module Stop Mode Setting
Address
Write signal
Compare match
signal
TGI interrupt
Buffer register
Compare register
φ
N
T
Buffer register address
1
Buffer register
write cycle
T
2
T
3
M
M
Buffer register write data