HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 357

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.3.6
SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also
used to selection of the transfer clock source. For details on interrupt requests, refer to section
14.8, Interrupts. Some bit functions of SCR differ between normal serial communication interface
mode and Smart Card interface mode.
Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit
7
6
5
4
3
2
Bit Name
TIE
RIE
TE
RE
MPIE
TEIE
Serial Control Register (SCR)
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
Transmit Enable
When this bit s set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Multiprocessor Interrupt Enable (enabled only when
the MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
and normal reception is resumed. For details, refer to
section 14.5, Multiprocessor Communication Function.
Transmit End Interrupt Enable
This bit is set to 1, TEI interrupt request is enabled.
Section 14 Serial Communication Interface (SCI)
Rev. 7.00 Sep. 11, 2009 Page 321 of 566
REJ09B0211-0700