HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 310

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 11 Motor Management Timer (MMT)
11.8
The port output enable (POE) circuit enables the MMT’s output pins (POUA, POUB, POVA,
POVB, POWA, POWB, and PCO) to be placed in the high-impedance state by varying the input
at pins POE0 to POE3. An interrupt can also be requested at the same time.
11.8.1
The POE circuit has the following features:
• Falling edge, φ/8 × 16 times, φ/16 × 16 times, or φ/128 × 16 times low-level sampling can be
• The MMT’s output pins can be placed in the high-impedance state on sampling of a falling
• An interrupt request can be initiated by input level sampling.
Rev. 7.00 Sep. 11, 2009 Page 274 of 566
REJ09B0211-0700
set for each of input pins POE0 to POE3.
edge or low level at pins POE0 to POE3.
POE3
POE2
POE1
POE0
Features
Port Output Enable (POE)
Input level detection circuit
Frequency divider
detection circuit
detection circuit
φ/8
Falling edge
Figure 11.21 Block Diagram of POE
Low level
φ
φ/16
ICSR
φ/128
High impedance request
control signal
Interrupt request