HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 291

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 11.3 shows the sample MMT canceling procedure.
Count Operation: Set 2Td (Td: value set in TDDR) as the initial value of the TCNT counter
when CST bit in TCNR is set to 0.
When the CST bit is set to 1, TCNT counts up to {value set in TPBR + 2Td}, and then starts
counting down. When TCNT reaches 2Td, it starts counting up again, and continues in this way.
TCNT is constantly compared with TGRU, TGRV, and TGRW. In addition, it is compared with
TGRUU, TGRVU, TGRWU, and TPDR when counting up, and with TGRUD, TGRVD,
TGRWD, and 2Td when counting down.
TDCNT0 to TDCNT5 are read-only counters. It is not necessary to set their initial values.
TDCNT0, TDCNT2, and TDCNT4 start counting up at the falling edge of a positive phase
compare match output when TCNT is counting down. When they become equal to TDDR they are
cleared to 0 and halt.
TDCNT1, TDCNT3, and TDCNT5 start counting up at the falling edge of a negative phase
compare match output when TCNT is counting up. When they match TDDR they are cleared to 0
and halt.
TDCNT0 to TDCNT5 are compared with TDDR only while a count operation is in progress. No
count operation is performed when the TDDR value is 0.
Figure 11.4 shows an example of the TCNT count operation.
Set external pin function
MMT count operation
Halt count operation
Set port
Figure 11.3 MMT Canceling Procedure
Set the PWM output port to go high.
Clear the enable bit in MMTPC to 0 to switch
the MMT output pin to the port pin.
Clear the CST bit in TCNR to 0 to halt count
operation.
Section 11 Motor Management Timer (MMT)
Rev. 7.00 Sep. 11, 2009 Page 255 of 566
REJ09B0211-0700