HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 128

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 PC Break Controller (PBC)
6.2.4
BCRB is the channel B break control register. The bit configuration is the same as for BCRA.
6.3
The operation flow from break condition setting to PC break interrupt exception handling is
shown in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break Interrupt
Due to Data Access, taking the example of channel A.
6.3.1
1. Set the break address in BARA.
2. Set the break conditions in BCR.
3. When the instruction at the set address is fetched, a PC break request is generated immediately
4. After priority determination by the interrupt controller, PC break interrupt exception handling
6.3.2
1. Set the break address in BARA.
2. Set the break conditions in BCRA.
3. After execution of the instruction that performs a data access on the set address, a PC break
4. After priority determination by the interrupt controller, PC break interrupt exception handling
Rev. 7.00 Sep. 11, 2009 Page 92 of 566
REJ09B0211-0700
For a PC break caused by an instruction fetch, set the address of the first instruction byte as the
break address.
Set bit 6 (CDA) to 0 to select the CPU because the bus master must be the CPU for a PC break
caused by an instruction fetch. Set the address bits to be masked to bits 3 to 5 (BAMA2 to
BAMA0). Set bits 1 and 2 (CSELA1 and CSELA0) to 00 to specify an instruction fetch as the
break condition. Set bit 0 (BIEA) to 1 to enable break interrupts.
before execution of the fetched instruction, and the condition match flag (CMFA) is set.
is started.
For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address
space address as the break address. Stack operations and branch address reads are included in
data accesses.
Select the bus master with bit 6 (CDA). Set the address bits to be masked to bits 3 to 5
(BAMA2 to BAMA0). Set bits 1 and 2 (CSELA1 and CSELA0) to 01, 10, or 11 to specify
data access as the break condition. Set bit 0 (BIEA) to 1 to enable break interrupts.
request is generated and the condition match flag (CMFA) is set.
is started.
Break Control Register B (BCRB)
PC Break Interrupt Due to Instruction Fetch
PC Break Interrupt Due to Data Access
Operation