HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 343

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

13.2.3
RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized
to H'1F by a reset signal from the RES pin, and not by the WDT internal reset signal caused by
overflows.
Bit
7
6
5
4 to
0
Note:
Bit Name
WOVF
RSTE
RSTS
—
* Only 0 can be written, for flag clearing.
Reset Control/Status Register (RSTCSR)
Initial Value
0
0
0
All 1
R/W
R/(W) *
R/W
R/W
—
Description
Watchdog Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode, and only 0 can be written.
[Setting condition]
•
[Clearing condition]
•
Reset Enable
Specifies whether or not a reset signal is generated
in the chip if TCNT overflows during watchdog timer
operation.
0: Reset signal is not generated even if TCNT
1: Reset signal is generated if TCNT overflows
Reset Select
Selects the type of internal reset generated if TCNT
overflows during watchdog timer operation.
0: Power-on reset
1: Setting prohibited
Reserved
These bits are always read as 1 and cannot be
modified.
overflows
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
Cleared by reading RSTCSR when WOVF = 1,
and then writing 0 to WOVF
Rev. 7.00 Sep. 11, 2009 Page 307 of 566
Section 13 Watchdog Timer
REJ09B0211-0700