HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 95

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.3
A reset has the highest exception priority.
When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this
LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during
operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the
CPU and the registers of on-chip supporting modules.
The chip can also be reset by overflow of the watchdog timer. For details see section 13,
Watchdog Timer.
The interrupt control mode is 0 immediately after reset.
4.3.1
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip supporting modules are
2.
Figures 4.1 and 4.2 show examples of the reset sequence.
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
execution starts from the address indicated by the PC.
The reset exception handling vector address is read and transferred to the PC, and program
Reset
Reset Exception Handling
Rev. 7.00 Sep. 11, 2009 Page 59 of 566
Section 4 Exception Handling
REJ09B0211-0700