HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 335

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

1. Set up the TPU channel to be used as the output trigger channel such that TGRA and TGRB
2. Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0
3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs,
4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by
are output compare registers. Set the trigger period in TGRB and the non-overlap margin in
TGRA, and set the counter to be cleared on compare match B. Set the TGIEA bit in TIER to 1
to enable the TGIA interrupt.
bits in PCR to select compare match in the TPU channel set up in the previous step to be the
output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output.
Write output data H'95 in NDRH.
outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0
to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt
handling routine writes the next output data (H'65) in NDRH.
writing H'59, H'56, H'95, ... at successive TGIA interrupts. If the DTC is set for activation by
this interrupt, pulse output can be obtained without imposing a load on the CPU.
Section 12 Programmable Pulse Generator (PPG)
Rev. 7.00 Sep. 11, 2009 Page 299 of 566
REJ09B0211-0700