HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 313

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit
7
6
5
4
3
2
Bit Name
POE3M1
POE3M0
POE2M1
POE2M0
POE1M1
POE1M0
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
POE3 Modes 1 and 0
These bits select the input mode of the POE3 pin.
00: Request accepted at falling edge of POE3 input
01: POE3 input is sampled for low level 16 times
10: POE3 input is sampled for low level 16 times
11: POE3 input is sampled for low level 16 times
POE2 Modes 1 and 0
These bits select the input mode of the POE2 pin.
00: Request accepted at falling edge of POE2 input
01: POE2 input is sampled for low level 16 times
10: POE2 input is sampled for low level 16 times
11: POE2 input is sampled for low level 16 times
POE1 Modes 1 and 0
These bits select the input mode of the POE1 pin.
00: Request accepted at falling edge of POE1 input
01: POE1 input is sampled for low level 16 times
10: POE1 input is sampled for low level 16 times
11: POE1 input is sampled for low level 16 times
every φ/8 clock, and request is accepted when
all samples are low level
every φ/16 clock, and request is accepted when
all samples are low level
every φ/128 clock, and request is accepted
when all samples are low level
every φ/8 clock, and request is accepted when
all samples are low level
every φ/16 clock, and request is accepted when
all samples are low level
every φ/128 clock, and request is accepted
when all samples are low level
every φ/8 clock, and request is accepted when
all samples are low level
every φ/16 clock, and request is accepted when
all samples are low level
every φ/128 clock, and request is accepted
when all samples are low level
Section 11 Motor Management Timer (MMT)
Rev. 7.00 Sep. 11, 2009 Page 277 of 566
REJ09B0211-0700