HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 440

IC H8S MCU FLASH 128K 80QFP

HD64F2612FA20

Manufacturer Part Number
HD64F2612FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2612FA20

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
43
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Price
Part Number:
HD64F2612FA20
Manufacturer:
RENESAS/瑞萨
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Section 15 Controller Area Network (HCAN)
Bit
7 to
5
4
3, 2
1
0
15.3.14 Receive Error Counter (REC)
The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating
the number of receive message errors on the CAN bus. The count value is stipulated in the CAN
protocol.
15.3.15 Transmit Error Counter (TEC)
The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter
indicating the number of transmit message errors on the CAN bus. The count value is stipulated in
the CAN protocol.
Rev. 7.00 Sep. 11, 2009 Page 404 of 566
REJ09B0211-0700
Bit Name
IMR12
IMR9
IMR8
Initial Value
All 1
1
All 1
1
1
R/W
R
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 1. Only 1 should be
written to these bits.
Bus Operation Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt
request by IRR12) is enabled. When set to 1,
OVR0 is masked.
Reserved
These bits are always read as 1. Only 1 should be
written to these bits.
Unread Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt
request by IRR9) is enabled. When set to 1, OVR0
is masked.
Mailbox Empty Interrupt Mask
When this bit is cleared to 0, SLE0 (interrupt
request by IRR8) is enabled. When set to 1, SLE0
is masked.

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