HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 203

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 10.3 CCLR0 to CCLR2 (channels 0 and 3)
Channel
0, 3
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1.
Table 10.4 CCLR0 to CCLR2 (channels 1, 2, 4, and 5)
Channel
1, 2, 4, 5
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
buffer register setting has priority, and compare match/input capture does not occur.
modified.
Bit 7
Reserved *
0
Bit 7
CCLR2
0
1
2
Bit 6
CCLR1
0
1
0
1
Bit 6
CCLR1
0
1
Bit 5
CCLR0
0
1
0
1
0
1
0
1
Bit 5
CCLR0
0
1
0
1
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
capture *
TCNT cleared by TGRD compare match/input
capture *
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *
Rev. 7.00 Sep. 11, 2009 Page 167 of 566
Section 10 16-Bit Timer Pulse Unit (TPU)
2
2
1
1
1
REJ09B0211-0700