HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 245

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.4.4
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow
of TCNT_2 (TCNT_5) as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 10.29 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
Table 10.29 Cascaded Combinations
Combination
Channels 1 and 2
Channels 4 and 5
Example of Cascaded Operation Setting Procedure: Figure 10.17 shows an example of the
setting procedure for cascaded operation.
and the counters operates independently in phase counting mode.
Cascaded Operation
<Cascaded operation>
Cascaded operation
Figure 10.17 Cascaded Operation Setting Procedure
Set cascading
Start count
Upper 16 Bits
TCNT_1
TCNT_4
[1]
[2]
[1]
[2]
Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'1111 to select TCNT_2
(TCNT_5) overflow/underflow counting.
Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
Rev. 7.00 Sep. 11, 2009 Page 209 of 566
Section 10 16-Bit Timer Pulse Unit (TPU)
Lower 16 Bits
TCNT_2
TCNT_5
REJ09B0211-0700