HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 405

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

after checking that the SCI has finished transmission, initialize the SCI, and set TE to 0 and RE to
1. Whether SCI has finished transmission or not can be checked with the TEND flag.
14.7.6
As data transmission in Smart Card interface mode involves error signal sampling and
retransmission processing, the operations are different from those in normal serial communication
interface mode (except for block transfer mode). Figure 14.26 illustrates the retransfer operation
when the SCI is in transmit mode.
1. If an error signal is sent back from the receiving end after transmission of one frame is
2. The TEND bit in SSR is not set for a frame in which an error signal indicating an abnormality
3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
Figure 14.28 shows a flowchart for transmission. The sequence of transmit operations can be
performed automatically by specifying the DTC to be activated with a TXI interrupt source. In a
transmit operation, the TDRE flag is set to 1 at the same time as the TEND flag in SSR is set, and
a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI request is
designated beforehand as a DTC activation source, the DTC will be activated by the TXI request,
and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically
cleared to 0 when data is transferred by the DTC. In the event of an error, the SCI retransmits the
same data automatically. During this period, the TEND flag remains cleared to 0 and the DTC is
not activated. Therefore, the SCI and DTC will automatically transmit the specified number of
bytes in the event of an error, including retransmission. However, the ERS flag is not cleared
automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an
ERI request will be generated in the event of an error, and the ERS flag will be cleared.
When performing transfer using the DTC, it is essential to set and enable the DTC before carrying
out SCI setting. For details of the DTC setting procedures, refer to section 8, Data Transfer
Controller (DTC).
complete, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next
parity bit is sampled.
is received. Data is retransferred from TDR to TSR, and retransmitted automatically.
Transmission of one frame, including a retransfer, is judged to have been completed, and the
TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt
request is generated. Writing transmit data to TDR transfers the next transmit data.
Data Transmission (Except for Block Transfer Mode)
Section 14 Serial Communication Interface (SCI)
Rev. 7.00 Sep. 11, 2009 Page 369 of 566
REJ09B0211-0700