HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 296

IC H8S MCU FLASH 128K 80QFP

HD64F2612FA20

Manufacturer Part Number
HD64F2612FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2612FA20

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
43
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2612FA20
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F2612FA20J
Manufacturer:
RENESAS/瑞萨
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Section 11 Motor Management Timer (MMT)
3. Output Generation Waveform
4. PWM Waveform
0% to 100% Duty Output: In the operating modes, PWM waveforms with any duty from 0% to
100% can be output. The output PWM duty is set using the buffer registers (TBRU to TBRW).
100% duty output is performed when the buffer register (TBRU to TBRW) value is set to H'0000.
The waveform in this case has positive phase in the 100% on state. 0% duty output is performed
when a value greater than the TPDR value is set as the buffer register (TBRU to TBRW) value.
The waveform in this case has positive phase in the 100% off state.
External Counter Clear Function: In the operating modes, the TCNT counter can be cleared
from an external source. When using the counter clear function, the PCI pin function should be set
to input using the MMT pin control register.
Rev. 7.00 Sep. 11, 2009 Page 260 of 566
REJ09B0211-0700
Output generation waveform U phase A (OGUA) is generated by ANDing CMOUA and
DTGUB, and output generation waveform U phase B (OGUB) is generated by ANDing
CMOUB and DTGUA.
The PWM waveform is generated by converting the output generation waveform to the output
level set in bits OLSN and OLSP in the timer mode register (TMDR).
Figure 11.6 shows an example of PWM waveform generation (operating mode 3, OLSN = 1,
OLSP = 1).
Dead time generation
Output generation
Compare output
PWM waveform
waveform
waveform
waveform
TPDR
2Td
Figure 11.6 Example of PWM Waveform Generation
When writing to free
operation address

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