HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 127

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.2.2
BARB is the channel B break address register. The bit configuration is the same as for BARA.
6.2.3
BCRA controls channel A PC breaks. BCRA also contains a condition match flag.
Bit
7
6
5
4
3
2
1
0
Bit Name
CMFA
CDA
BAMRA2
BAMRA1
BAMRA0
CSELA1
CSELA0
BIEA
Break Address Register B (BARB)
Break Control Register A (BCRA)
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
[Setting condition]
•
[Clearing condition]
•
CPU Cycle/DTC Cycle Select A
Selects the channel A break condition bus master.
0: CPU
1: CPU or DTC
Break Address Mask Register A2 to A0
These bits specify which bits of the break address set in
BARA are to be masked.
000: BAA23 to 0 (All bits are unmasked)
001: BAA23 to 1 (Lowest bit is masked)
010: BAA23 to 2 (Lower 2 bits are masked)
011: BAA23 to 3 (Lower 3 bits are masked)
100: BAA23 to 4 (Lower 4 bits are masked)
101: BAA23 to 8 (Lower 8 bits are masked)
110: BAA23 to 12 (Lower 12 bits are masked)
111: BAA23 to 16 (Lower 16 bits are masked)
Break Condition Select A
Selects break condition of channel A.
00: Instruction fetch is used as break condition
01: Data read cycle is used as break condition
10: Data write cycle is used as break condition
11: Data read/write cycle is used as break condition
When this bit is 1, the PC break interrupt request of
channel A is enabled.
Condition Match Flag A
Break Interrupt Enable A
When a condition set for channel A is satisfied
When 0 is written to CMFA after reading CMFA = 1
Rev. 7.00 Sep. 11, 2009 Page 91 of 566
Section 6 PC Break Controller (PBC)
REJ09B0211-0700