HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 89

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3.2.2
SYSCR is an 8-bit readable/writable register that selects saturating or non-saturating calculation
for the MAC instruction, selects the interrupt control mode and the detected edge for NMI, and
enables or disables on-chip RAM.
Bit
7
6
5
4
3
2, 1
0
Bit Name
MACS
—
INTM1
INTM0
NMIEG
—
RAME
System Control Register (SYSCR)
Intial Value
0
0
0
0
0
All 0
1
—
R/W
R/W
—
R/W
R/W
R/W
—
Descriptions
MAC Saturation
Selects either saturating or non-saturating calculation
for the MAC instruction.
0: Non-saturating calculation for the MAC instruction
1: Saturating calculation for the MAC instruction
Reserved
This bit is always read as 0 and cannot be modified.
These bits select the control mode of the interrupt
controller. For details of the interrupt control modes,
see section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Setting prohibited
10: Interrupt control mode 2
11: Setting prohibited
NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
1: An interrupt is requested at the rising edge of NMI
Reserved
These bits are always read as 0 and cannot be
modified.
RAM Enable
Enables or disables on-chip RAM. The RAME bit is
initialized when the reset status is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
input
input
Rev. 7.00 Sep. 11, 2009 Page 53 of 566
Section 3 MCU Operating Modes
REJ09B0211-0700