LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 97

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
a. 32 bit wide memory bank interfaced to four 8 bit memory chips
b. 32 bit wide memory bank interfaced to two 16 bit memory chips
A[a_b:2]
CS
OE
D[31:24]
11.1 32-bit wide memory bank connection
BLS[3]
Symbol "a_b" in the following figures refers to the highest order address line in the data
bus. Symbol "a_m" refers to the highest order address line of the memory chip used in the
external memory interface.
If the external memory is used as external boot memory for flashless devices, refer to
Section 8–6
and 2 is determined by the setting of the two BOOT1/0 pins.
CE
OE
WE
IO[7:0]
A[a_m:0]
A[a_b:2]
WE
OE
CS
on how to connect the EMC. The memory bank width for memory banks 1
D[23:16]
D[31:16]
BLS[2]
BLS[3]
BLS[2]
Rev. 04 — 26 August 2009
CE
OE
WE
IO[7:0]
A[a_m:0]
CE
OE
WE
UB
LB
IO[15:0]
A[a_m:0]
Chapter 5: LPC24XX External Memory Controller (EMC)
D[15:8]
D[15:0]
BLS[1]
BLS[0]
BLS[1]
CE
OE
WE
UB
LB
IO[15:0]
A[a_m:0]
CE
OE
WE
IO[7:0]
A[a_m:0]
BLS[0]
D[7:0]
UM10237
© NXP B.V. 2009. All rights reserved.
CE
OE
WE
IO[7:0]
A[a_m:0]
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