LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 107

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
8. MAM usage notes
UM10237_4
User manual
Fig 21. Block diagram of the Memory Accelerator Module
ADDR
[18:4]
EQPREF
MUX
=
ADDR
LA[3:2]
ENAL0
cclk
INCREMENTOR
ENP
When changing MAM timing, the MAM must first be turned off by writing a zero to
MAMCR. A new value may then be written to MAMTIM. Finally, the MAM may be turned
on again by writing a value (1 or 2) corresponding to the desired operating mode to
MAMCR.
For a system clock slower than 20 MHz, MAMTIM can be 001. For a system clock
between 20 MHz and 40 MHz, flash access time is suggested to be 2 CCLKs, while in
systems with a system clock faster than 40 MHz, 3 CCLKs are proposed. For system
clocks of 60 MHz and above, 4CCLK’s are needed.
D
EN
EQA0
PREFETCH LATCH
=
PREFETCH MUX
Q
128
32
xFFE0
0FFF0
30000
20000
10000
00020
00010
00000
Rev. 04 — 26 August 2009
EQBT
=
xFFE4
0FFF4
30004
20004
10004
00024
00014
00004
ADDR
Chapter 6: LPC24XX Memory Accelerator Module (MAM)
128
xFFE8
0FFF8
30008
20008
10008
00028
00018
00008
ENBT
DI[31:0] (to ARM core)
FINAL MUX
BT LATCH
xFFEC
3000C
2000C
1000C
0FFFC
0002C
0001C
0000C
128
BT MUX
32
EQD
=
ADDR
UM10237
END
© NXP B.V. 2009. All rights reserved.
DATA LATCH
DATA MUX
128
32
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