LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 570

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
6.12 Clear Register (MCIClear - 0xE008 C038)
6.13 Interrupt Mask Registers (MCIMask0 - 0xE008 C03C)
Table 504: Status register (MCIStatus - address 0xE008 C034) bit description
The MCIClear register is a write-only register. The corresponding static status flags can be
cleared by writing a 1 to the corresponding bit in the register.
assignment of the MCIClear register.
Table 505: Clear register (MCIClear - address 0xE008 C038) bit description
The interrupt mask registers determine which status flags generate an interrupt request by
setting the corresponding bit to 1.
MCIMaskx registers.
Table 506: Interrupt Mask registers (MCIMask0 - address 0xE008 C03C) bit description
Bit
20
21
31:22
Bit
0
1
2
3
4
5
6
7
8
9
10
31:11
Bit
0
1
2
3
4
5
6
7
Symbol
TxDataAvlbl
RxDataAvlbl
-
Symbol
CmdCrcFailClr
DataCrcFailClr
CmdTimeOutClr
DataTimeOutClr
TxUnderrunClr
RxOverrunClr
CmdRespEndClr
CmdSentClr
DataEndClr
StartBitErrClr
DataBlockEndClr
-
Symbol
Mask0
Mask1
Mask2
Mask3
Mask4
Mask5
Mask6
Mask7
Rev. 04 — 26 August 2009
Description
Data available in transmit FIFO.
Data available in receive FIFO.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
Mask CmdCrcFail flag.
Mask DataCrcFail flag.
Mask CmdTimeOut flag.
Mask DataTimeOut flag.
Mask TxUnderrun flag.
Mask RxOverrun flag.
Mask CmdRespEnd flag.
Mask CmdSent flag.
Clears RxOverrun flag.
Description
Clears CmdCrcFail flag.
Clears DataCrcFail flag.
Clears CmdTimeOut flag.
Clears DataTimeOut flag.
Clears TxUnderrun flag.
Clears CmdRespEnd flag.
Clears CmdSent flag.
Clears DataEnd flag.
Clears StartBitErr flag.
Clears DataBlockEnd flag.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Table 21–506
Chapter 21: LPC24XX SD/MMC card interface
shows the bit assignment of the
Table 21–505
UM10237
© NXP B.V. 2009. All rights reserved.
shows the bit
Reset
Value
0
0
NA
Reset
Value
0
0
0
0
0
0
0
0
570 of 792
Reset
Value
-
-
-
-
-
-
-
-
-
-
-
NA