LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 561

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
5.3.12 CRC generator
5.3.13 Data FIFO
5.3.11 Status flags
Table 21–487
(MCIStatus - 0xE008 C034)” on page 569
Table 487. Data path status flags
The CRC generator calculates the CRC checksum only for the data bits in a single block,
and is bypassed in data stream mode. The checksum is a 16 bit value:
The data FIFO (first-in-first-out) subunit is a data buffer with transmit and receive logic.
The FIFO contains a 32 bit wide, 16-word deep data buffer, and transmit and receive
logic. Because the data FIFO operates in the APB clock domain (PCLK), all signals from
the subunits in the MCI clock domain (MCLK) are resynchronized.
Depending on TxActive and RxActive, the FIFO can be disabled, transmit enabled, or
receive enabled. TxActive and RxActive are driven by the data path subunit and are
mutually exclusive:
Flag
TxFifoFull
TxFifoEmpty
TxFifoHalfEmpty
TxDataAvlbl
TxUnderrun
RxFifoFull
RxFifoEmpty
RxFifoHalfFull
RxDataAvlbl
RxOverrun
DataBlockEnd
StartBitErr
DataCrcFail
DataEnd
DataTimeOut
TxActive
RxActive
•
CRC[15:0] = Remainder [(M(x) × x
G(x) = x
M(x) - (first data bit) × x
The transmit FIFO refers to the transmit logic and data buffer when TxActive is
asserted (see
16
+ x
lists the data path status flags (see
12
Section 21–5.3.14 “Transmit
+ x
5
Rev. 04 — 26 August 2009
+ 1
n
+ ... + (last data bit) ¥ X
Description
Transmit FIFO is full.
Transmit FIFO is empty.
Transmit FIFO is half full.
Transmit FIFO data available.
Transmit FIFO underrun error.
Receive FIFO is full.
Receive FIFO is empty.
Receive FIFO is half full.
Receive FIFO data available.
Receive FIFO overrun error.
Data block sent/received.
Start bit not detected on all data signals in wide bus mode.
Data packet CRC failed.
Data end (data counter is zero).
Data timeout.
Data transmission in progress.
Data reception in progress.
15
) / G(x)]
Chapter 21: LPC24XX SD/MMC card interface
for more information).
FIFO”)
Section 21–6.11 “Status Register
0
UM10237
© NXP B.V. 2009. All rights reserved.
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