LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 247

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
9. Ethernet block functional description
UM10237_4
User manual
9.1 Overview
Table 241. Transmit status information word
For multi-fragment frames, the value of the LateCollision, ExcessiveCollision,
ExcessiveDefer, Defer and CollissionCount bits in all but the last fragment in the frame will
be 0. The status of the last fragment in the frame will copy the value for these bits from the
MAC. All fragment statuses will have valid Error, NoDescriptor and Underrun bits.
This section defines the functions of the DMA capable 10/100 Ethernet MAC. After
introducing the DMA concepts of the Ethernet block, and a description of the basic
transmit and receive functions, this section elaborates on advanced features such as flow
control, receive filtering, etc.
The Ethernet block can transmit and receive Ethernet packets from an off-chip Ethernet
PHY connected through the MII or RMII interface. MII or RMII mode can be selected from
software.
Typically during system start-up, the Ethernet block will be initialized. Software
initialization of the Ethernet block should include initialization of the descriptor and status
arrays as well as the receiver fragment buffers.
To transmit a packet the software driver has to set up the appropriate Control registers
and a descriptor to point to the packet data buffer before transferring the packet to
hardware by incrementing the TxProduceIndex register. After transmission, hardware will
increment TxConsumeIndex and optionally generate an interrupt.
The hardware will receive packets from the PHY and apply filtering as configured by the
software driver. While receiving a packet the hardware will read a descriptor from memory
to find the location of the associated receiver data buffer. Receive data is written in the
Bit
20:0
24:21 CollisionCount
25
26
27
28
29
30
31
Symbol
-
Defer
ExcessiveDefer
ExcessiveCollision Indicates this packet exceeded the maximum collision limit and was
LateCollision
Underrun
NoDescriptor
Error
Rev. 04 — 26 August 2009
Description
Unused
The number of collisions this packet incurred, up to the
Retransmission Maximum.
This packet incurred deferral, because the medium was occupied.
This is not an error unless excessive deferral occurs.
This packet incurred deferral beyond the maximum deferral limit and
was aborted.
aborted.
An Out of window Collision was seen, causing packet abort.
A Tx underrun occurred due to the adapter not producing transmit
data.
The transmit stream was interrupted because a descriptor was not
available.
An error occurred during transmission. This is a logical OR of
Underrun, LateCollision, ExcessiveCollision, and ExcessiveDefer.
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
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