LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 531

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
7. Register description
UM10237_4
User manual
7.1 SPI Control Register (S0SPCR - 0xE002 0000)
The SPI contains 5 registers as shown in
and word accessible.
Table 461. SPI register map
[1]
The S0SPCR register controls the operation of the SPI0 as per the configuration bits
setting.
Table 462: SPI Control Register (S0SPCR - address 0xE002 0000) bit description
Name
S0SPCR
S0SPSR
S0SPDR
S0SPCCR SPI Clock Counter Register. This register
S0SPINT
Bit
1:0
2
3
4
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Symbol
-
BitEnable
CPHA
CPOL
Description
SPI Control Register. This register controls the
operation of the SPI.
SPI Status Register. This register shows the
status of the SPI.
SPI Data Register. This bi-directional register
provides the transmit and receive data for the
SPI. Transmit data is provided to the SPI0 by
writing to this register. Data received by the SPI0
can be read from this register.
controls the frequency of a master’s SCK0.
SPI Interrupt Flag. This register contains the
interrupt flag for the SPI interface.
Value Description
0
1
0
1
0
1
Rev. 04 — 26 August 2009
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
The SPI controller sends and receives 8 bits of data per
transfer.
The SPI controller sends and receives the number of bits
selected by bits 11:8.
Clock phase control determines the relationship between
the data and the clock on SPI transfers, and controls
when a slave transfer is defined as starting and ending.
Data is sampled on the first clock edge of SCK. A transfer
starts and ends with activation and deactivation of the
SSEL signal.
Data is sampled on the second clock edge of the SCK. A
transfer starts with the first clock edge, and ends with the
last sampling edge when the SSEL signal is active.
Clock polarity control.
SCK is active high.
SCK is active low.
Table
19–461. All registers are byte, half word
Access
R/W
RO
R/W
R/W
R/W
Chapter 19: LPC24XX SPI
Reset
Value
0x00
0x00
0x00
0x00
0x00
UM10237
© NXP B.V. 2009. All rights reserved.
[1]
Address
0xE002 0000
0xE002 0004
0xE002 0008
0xE002 000C
0xE002 001C
Reset
Value
NA
0
0
0
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