LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 724

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
6.1.8 Enabled Channel Register (DMACEnbldChns - 0xFFE0 401C)
6.1.9 Software Burst Request Register (DMACSoftBReq - 0xFFE0 4020)
Table 659. Raw Error Interrupt Status register (DMACRawIntErrorStatus - address
The DMACEnbldChns Register is read-only and indicates which DMA channels are
enabled, as indicated by the Enable bit in the DMACCxConfiguration Register. A HIGH bit
indicates that a DMA channel is enabled. A bit is cleared on completion of the DMA
transfer.
Table 660. Enabled Channel register (DMACEnbldChns - address 0xFFE0 401C) bit
The DMACSoftBReq Register is read/write and enables DMA burst requests to be
generated by software. A DMA request can be generated for each source by writing a 1 to
the corresponding register bit. A register bit is cleared when the transaction has
completed. Writing 0 to this register has no effect. Reading the register indicates which
sources are requesting DMA burst transfers. A request can be generated from either a
peripheral or the software request register.
DMACSoftBReq Register.
Table 661. Software Burst Request register (DMACSoftBReq - address 0xFFE0 4020) bit
Note: It is recommended that software and hardware peripheral requests are not used at
the same time.
Bit
0
1
31:2
Bit
0
1
31:2
Bit
0
1
2
3
4
5
6
31:7
Symbol
RawIntErrorStatus0 Status of the error interrupt for channel 0 prior to masking.
RawIntErrorStatus1 Status of the error interrupt for channel 1 prior to masking.
-
Symbol
EnabledChannels0 Enable status for Channel 0.
EnabledChannels1 Enable status for Channel 1.
-
Symbol
SoftBReqSSP0Tx
SoftBReqSSP0Rx
SoftBReqSSP1Tx
SoftBReqSSP1Rx
SoftBReqSDMMC
SoftBReqI2S0
SoftBReqI2S1
-
Table 32–660
0xFFE0 4018) bit description
description
description
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
shows the bit assignments of the DMACEnbldChns Register.
Description
Software burst request flag for SSP0 Tx.
Software burst request flag for SSP0 Rx.
Software burst request flag for SSP1 Tx.
Software burst request flag for SSP1 Rx.
Software burst request flag for SD/MMC.
Software burst request flag for I
Software burst request flag for I
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Table 32–661
2
2
S0.
S1.
shows the bit assignments of the
UM10237
© NXP B.V. 2009. All rights reserved.
724 of 792
Reset
Value
0
0
0
0
0
0
0
NA
Reset
Value
-
-
NA
Reset
Value
0
0
NA