LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 431

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
4.6 UARTn FIFO Control Register (U0FCR - 0xE000 C008, U2FCR -
4.7 UARTn Line Control Register (U0LCR - 0xE000 C00C, U2LCR -
THRE = 1 and there have not been at least two characters in the UnTHR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
UnTHR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UARTn THR FIFO has held two or more characters at one time and
currently, the UnTHR is empty. The THRE interrupt is reset when a UnTHR write occurs or
a read of the UnIIR occurs and the THRE is the highest interrupt (UnIIR[3:1] = 001).
0xE007 8008, U3FCR - 0xE007 C008, Write Only)
The UnFCR controls the operation of the UARTn Rx and TX FIFOs.
Table 385. UARTn FIFO Control Register (U0FCR - address 0xE000 C008,
0xE007 800C, U3LCR - 0xE007 C00C)
The UnLCR determines the format of the data character that is to be transmitted or
received.
Bit
0
1
2
5:3
7:6
Symbol
FIFO Enable 0
RX FIFO
Reset
TX FIFO
Reset
-
RX Trigger
Level
U2FCR - 0xE007 8008, U3FCR - 0xE007 C008, Write Only) bit description
Value
1
0
1
0
1
0
00
01
10
11
Rev. 04 — 26 August 2009
Description
UARTn FIFOs are disabled. Must not be used in the
application.
Active high enable for both UARTn Rx and TX
FIFOs and UnFCR[7:1] access. This bit must be set
for proper UARTn operation. Any transition on this
bit will automatically clear the UARTn FIFOs.
No impact on either of UARTn FIFOs.
Writing a logic 1 to UnFCR[1] will clear all bytes in
UARTn Rx FIFO and reset the pointer logic. This bit
is self-clearing.
No impact on either of UARTn FIFOs.
Writing a logic 1 to UnFCR[2] will clear all bytes in
UARTn TX FIFO and reset the pointer logic. This bit
is self-clearing.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
These two bits determine how many receiver
UARTn FIFO characters must be written before an
interrupt is activated.
Trigger level 0 (1 character or 0x01)
Trigger level 1 (4 characters or 0x04)
Trigger level 2 (8 characters or 0x08)
Trigger level 3 (14 characters or 0x0E)
Chapter 16: LPC24XX UART0/2/3
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
0
0
0
NA
0
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