LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 602

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
9.12.1 Initialization
9.12 I
This section provides examples of operations that must be performed by various I
service routines. This includes:
In the initialization example, the I
For each mode, a buffer is used for transmission and reception. The initialization routine
performs the following functions:
2
Fig 125. Forced access to a busy I
Fig 126. Recovering from a bus obstruction caused by a low level on SDA
•
•
•
•
•
•
C State service routines
Initialization of the I
I
The 26 state service routines providing support for all four I
I2ADR is loaded with the part’s own slave address and the general call bit (GC).
The I
The slave mode is enabled by simultaneously setting the I2EN and AA bits in I2CON
and the serial clock frequency (for master modes) is defined by loading CR0 and CR1
in I2CON. The master routines must be started in the main program.
2
C Interrupt Service.
(1) Unsuccessful attempt to send a start condition.
(2) SDA line is released.
(3) Successful attempt to send a start condition. State 08H is entered.
2
C interrupt enable and interrupt priority bits are set.
STO flag
SDA line
STA flag
SCL line
STA flag
SDA line
SCL line
Rev. 04 — 26 August 2009
2
C block after a Reset.
(1)
time limit
2
C block is enabled for both master and slave modes.
2
C bus
(1)
Chapter 22: LPC24XX I
(2)
condition
(3)
start
condition
start
2
C operating modes.
2
C interfaces I
UM10237
© NXP B.V. 2009. All rights reserved.
602 of 792
2
2
C state
C0/1/2