LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 731
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
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LPC2458FET180,551
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Table 674. Channel Configuration registers (DMACC0Configuration - address 0xFFE0 4110 and
UM10237_4
User manual
Bit
0
Symbol
E
DMACC1Configuration - address 0xFFE0 4130) bit description
6.2.6 Channel Configuration Registers (DMACC0Configuration - 0xFFE0 4110 and
Value Description
0
1
Table 673. Protection bits
DMACC1Configuration - 0xFFE0 4130)
The two DMACCxConfiguration Registers are read/write with the exception of bit[17]
which is read-only. Used these to configure the DMA channel. The registers are not
updated when a new LLI is requested.
DMACCxConfiguration Register.
DMACC1Control
Bit
30
The Channel Enable bit status can also be found by reading the DMACEnbldChns
Register.
A channel is enabled by setting this bit.
A channel can be disabled by clearing the Enable bit. This causes the current AHB
transfer (if one is in progress) to complete and the channel is then disabled. Any
data in the FIFO of the relevant channel is lost. Restarting the channel by setting the
Channel Enable bit has unpredictable effects and the channel must be fully
re-initialized.
The channel is also disabled, and Channel Enable bit cleared, when the last LLI is
reached or if a channel error is encountered.
If a channel has to be disabled without losing data in the FIFO the Halt bit must be
set so that further DMA requests are ignored. The Active bit must then be polled
until it reaches 0, indicating that there is no data left in the FIFO. Finally the Channel
Enable bit can be cleared.
Channel enable -- reading this bit indicates whether a channel is currently enabled
or disabled:
Channel disabled.
Channel enabled.
Value Description
0
1
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
Cacheable or not cacheable. This indicates that the access is
cacheable. This bit can, for example, be used to indicate to an
AMBA bridge that when it saw the first read of a burst of eight it
can transfer the whole burst of eight reads on the destination
bus, rather than pass the transactions through one at a time.
This bit controls the AHB HPROT[3] signal.
Indicates that the access is cacheable or not cacheable:
Not cacheable.
Cacheable.
Table 32–674
shows the bit assignments of the
UM10237
© NXP B.V. 2009. All rights reserved.
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